r03ds0065ej0200 rev.2.00 page 1 of 7 jul 03, 2012 preliminary datasheet rna50c27aus cmos system-reset ic description this ic facilitates complicated power-on and power-monitoring resets of micr ocomputers that require the 3.3-v and 1.8-v dual power supplies. it also facilitates change of delay time of reset signal by externally setting resistance and capacity for delay time. by employing complementary open-drain output, desired output such as open-drain output and cmos output can be obtained. functions ? 3.3-v detection voltage : 2.7 v ? accuracy of 3.3-v detection voltage : ? 1.0% ? hysteresis of 3.3-v detection voltage : 5% typ. ? open-drain/cmos output ? 1.8-v pmos drive output ? ultra-small sso p-8 package ordering information part name package type package code package abbreviation taping abbreviation (quantity) surface treatment rna50c27ausel-e ssop-8 pvsp0008ka-a us el (3,000 pcs / reel) e (sn-bi) block diagram ? + 1 8 mr vdd33 2 resp 3 res n 6 vdd18 vref delay 7 crext 4 gnd 5 swg r03ds0065ej0200 rev.2.00 jul 03, 2012
rna50c27aus preliminary r03ds0065ej0200 rev.2.00 page 2 of 7 jul 03, 2012 pin arrangement 18 4 3 2 mr swg (top view) vdd18 crext 6 7 5 vdd33 resn resp gnd pin description pin no. pin name function 1 vdd33 input power supply pin for 3.3-v voltage. re commended operating range is 2.7 to 3.6 v. set the input voltage to 0.033 v/ ? s or less when starting up. 2 resp active-low reset signal output pin. by conne cting to resn pin, cmos output can be used. if using open-drain, please connect pull-down resistor. 3 resn active-low reset signal output pin. by conne cting to resp pin, cmos output can be used. if using open-drain, please connect pull-up resistor. 4 gnd gnd pin 5 swg external pmos gate control signal to be set between 1.8-v power supply and 1.8-v voltage input of microcomputer. 6 vdd18 input power supply pin for 1.8-v voltage. recommended operating range is 1.65 to 3.6 v. 7 crext connecting pin for rext resistance and cext c apacity that determine the delay time of reset signal. 3.3 k ? or more is recommended for resistance. the delay time, t dly , is given by the following formula. t dly = cext ? rext [s] 8 mr pin to provide reset manually. mr pin is pulled-up to vdd33 through internal resistor.
rna50c27aus preliminary r03ds0065ej0200 rev.2.00 page 3 of 7 jul 03, 2012 absolute maximum ratings item symbol ratings unit vdd33 4.6 supply voltage vdd18 4.6 v input voltage v i ?0.3 to vdd33+0.3 v output voltage v o ?0.3 to vdd33+0.3 v input current i i 20 ma output current i o 25 ma supply current i dd 25 ma power dissipation p t 273 mw storage temperature tstg ?55 to +125 c recommended operating conditions item symbol min typ max unit remarks vdd33 vth33 ? 3.6 supply voltage vdd18 1.65 ? vdd33 v input voltage v mr 0 ? vdd33 v v o 0 ? vdd33 output voltage v oswg 0 ? vdd18 v external resistor rext 3.3 ? ? k ? vdd33 = 3.3 v external capacitor cext ? no limit ? drivable capacitor c l ? 2200 ? pf swg output operating temperature ta ?40 ? 85 c
rna50c27aus preliminary r03ds0065ej0200 rev.2.00 page 4 of 7 jul 03, 2012 electrical characteristics dc characteristics (vdd33 = 3.3 v, vdd18 = 1.8 v, ta = 25c, crext:r = 10 k ? ) item symbol min typ m ax unit test conditions idd33 0.75 1.5 4 quiescent supply current idd18 0.25 0.5 2 ? a all outputs are open vth33 typ ? 0.99 2.7 typ?1.01 vth h 1.2 ? ? detection voltage vth l ? ? 0.55 v detection voltage temperature dependency vth33 vth?ta ? ? 100 ? ppm/c detection voltage hysteresis v hys vth33 ? 3% vth33 ? 5% vth33 ? 8% v low-level input voltage v il ? ? vth33 ? 0.25 v high-level input voltage v ih vth33 ? 0.75 ? ? v mr internal pull-up resistance r mr ? t.b.d. ? k ? low-level output current i ol 7.5 15 30 v o = 0.5 v cmos * 1 high-level output current i oh 5 10 20 ma v o = vdd33 ? 0.5 v resp output leakage current i leak ? ? 0.1 ? a resn off resn output leakage current i leak ? ? 0.1 ? a resp off high-level output voltage v oh 1.7 ? ? v v o = open output source current i oh 1.5 3 6 ma v o = vdd33 ? 0.5 v low-level output voltage v ol ? ? 0.1 v v o = open swg output sink current i ol 0.2 0.35 0.55 ma v o = 0.5 v note: when the voltage within v il < v in < v ih is applied to mr and vdd18 inpu t by dc, oscillation may occur. 1. when resp output and resn shor t out and cmos output is used. ac characteristics item symbol min typ m ax unit test conditions tp lh ? 50 400 propagation delay time tp hl ? 5 t.b.d. ? s c l = 15 pf, crext:c = open t r ? 5 t.b.d. ns resp response time t f ? 5 t.b.d. ? s c l = 15 pf tp lh ? 50 400 propagation delay time tp hl ? 1.5 t.b.d. ? s c l = 15 pf, crext:c = open t r ? 5 t.b.d. ? s resn response time t f ? 5 t.b.d. ns c l = 15 pf tp lh ? 50 400 propagation delay time tp hl t.b.d. 1.5 t.b.d. ? s t r t.b.d. 1.0 t.b.d. swg response time t f t.b.d. 7.6 t.b.d. ? s c l = 2200 pf delay time t dly ? 93 ? ms crext:c = 0.1 ? f, r = 1 m ?
rna50c27aus preliminary r03ds0065ej0200 rev.2.00 page 5 of 7 jul 03, 2012 timing chart vth33 vdd33 t dly t dly vdd18 res swg mr t dly t dly t dly t dly vrel vth18 vopmin
rna50c27aus preliminary r03ds0065ej0200 rev.2.00 page 6 of 7 jul 03, 2012 package dimensions 2.4 0.80.7 1.8 2.2 0.6 a l e e c 1 b 1 d e a 2 b p c x y h e z l 1 2.0 (0.4) 3.1 0.08 0.13 0.23 0.3 0 0.1 2.3 reference symbol dimension in millimeters min nom max 2.2 a 1 0.15 0.22 3.4 2.8 (0.5) 0.11 0.20 p f 1 e 4 85 b h e 0.17 () d 1.5 0.2 1 1 terminal cross section p b c c b detail f 1 2 1 l a a p-vssop8-2.3x2-0.50 0.010g mass[typ.] ttp-8db/ttp-8dbv pvsp0008ka-a renesas code jeita package code previous code footprint unit: mm these numbers on the diagram are reference values. please adjust size, space, and other area of footprint as needed. note: ssop-8 footprint example 0.5 0.3 0.5 0.5 0.2 0.1 0.4 2.3 3.1
rna50c27aus preliminary r03ds0065ej0200 rev.2.00 page 7 of 7 jul 03, 2012 taping and reel specifications wp 1 a 0 k 0 f maximum storage no. reel type packing form 4 1.0 1.05 3,000 ic/reel w 1 w 2 13.0 9.0 8 tape width: w [taping] [reel] 8 2.25 3.4 3.5 c non dry pack b 0 d 1 unit: mm 13 0.5 178 2 w 1 w 2 2.0 0.5 4 0.5 reel type: c 120 d 1 p 1 0.3 1.5 a 0 w f1.75 42 b 0 k 0
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